What is hazard in the pipeline? Explain hazard avoidance methods...

Pipeline Hazards and Hazard Avoidance Methods (B.Tech CSE)

In a pipelined processor, multiple instructions overlap in different stages (like IF, ID, EX, MEM, WB). A hazard is any situation that prevents the next instruction in the pipeline from executing in its intended cycle. Hazards reduce throughput by introducing bubbles (stalls) or by causing incorrect execution if not handled.

Types of Pipeline Hazards

Structural Hazards: Two or more pipeline stages need the same hardware resource at the same time (e.g., a single memory used for both instruction fetch and data access).
Data Hazards: An instruction depends on the result of a previous instruction.
- RAW (Read After Write): True dependency; consumer needs a value not yet produced.
- WAR (Write After Read): Anti-dependency; a later write might overwrite before an earlier read completes (in out-of-order designs).
- WAW (Write After Write): Output dependency; two writes to the same register may commit in the wrong order (in out-of-order designs).
Control Hazards: Arise from branches, jumps, and exceptions; the pipeline doesn’t know the correct next PC until the branch is resolved.

Quick Example

5-stage pipeline: IF | ID | EX | MEM | WB

I1: LW   R1, 0(R2)      ; loads R1
I2: ADD  R3, R1, R4     ; uses R1 (RAW hazard with I1)
I3: SW   R3, 0(R5)      ; uses R3 (depends on I2)
I4: BEQ  R3, R0, Target ; control hazard (branch)
I5: SUB  R6, R7, R8     ; may be fetched before branch resolves

Hazard Avoidance and Handling Methods

1) Structural Hazard Avoidance

Duplicate or partition resources: Use separate instruction and data memories (Harvard architecture) or multi-ported caches to allow concurrent access.
Pipeline-friendly resource design: Balance stage latencies and avoid sharing single-cycle units when possible.
Arbitration and scheduling: If sharing is unavoidable, hardware schedules access and may stall one instruction minimally.

2) Data Hazard Avoidance

Forwarding/Bypassing: Send the computed result directly from EX/MEM/WB pipeline registers to earlier stages that need it, instead of waiting for WB. This removes most RAW stalls (except load-use).
Load-Use Interlock (one-cycle stall): If an instruction uses a value immediately after a load, insert a bubble because the loaded data is only available after MEM.
Pipeline Interlocks (Hazard Detection Unit): Hardware detects dependencies and automatically inserts the minimum necessary stalls when forwarding can’t fix the hazard.
Compiler Scheduling: Reorder independent instructions to fill delay slots and avoid stalls; insert NOPs only if no useful reordering exists.
Register Renaming: Eliminate WAR and WAW by mapping logical registers to different physical registers; essential in out-of-order cores.
Out-of-Order Execution with Reservation Stations (advanced): Issue independent instructions early and complete them as operands become ready while preserving program order at commit.

3) Control Hazard Avoidance

Early Branch Resolution: Move branch comparison and target calculation to earlier pipeline stages (e.g., ID) to reduce penalty.
Static Branch Prediction: Simple policies like “predict not taken,” “backward taken, forward not taken,” or compiler-provided hints.
Dynamic Branch Prediction: Hardware predictors (1-bit/2-bit saturating counters, gshare, TAGE) use history to guess the branch direction.
Branch Target Buffer (BTB): Caches target addresses so fetching can continue immediately along the predicted path.
Speculative Execution with Flush: Fetch and execute along the predicted path; if the prediction is wrong, flush incorrect instructions and redirect the PC.
Delayed Branching (in some RISC designs): One or more delay slots after the branch are always executed; the compiler fills them with useful work.
Predication/If-Conversion: Convert small conditional blocks into conditionally executed instructions to avoid branches.

Putting It All Together (Typical Pipeline Strategy)

Use separate instruction/data memories or multi-ported cache to remove structural conflicts.
Implement forwarding paths and a hazard detection unit; stall only for load-use cases that forwarding can’t solve.
Adopt static or dynamic branch prediction with BTB and early branch resolution; flush on misprediction.
Let the compiler perform instruction scheduling; advanced CPUs add register renaming and out-of-order execution to reduce remaining stalls.

Summary

A hazard in a pipeline is any condition that prevents the next instruction from advancing in its normal cycle. The main categories are structural, data, and control hazards. Processors avoid or mitigate hazards using a mix of architectural (forwarding, renaming, prediction) and compiler techniques (reordering, filling delay slots), aiming to keep the pipeline busy and maintain correct program execution.

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