Draw the seven-stage instruction pipeline.
Seven-Stage Instruction Pipeline Diagram
The following ASCII diagram shows a typical seven-stage RISC instruction pipeline used in advanced computer architecture. It separates fetch, decode, execute, memory, and write-back into fine-grained steps for higher clock speeds.
Linear pipeline stages: +-----+ +-----+ +-----+ +-----+ +------+ +------+ +-----+ | IF1 |-->| IF2 |-->| ID |-->| EX |-->| MEM1 |-->| MEM2 |-->| WB | +-----+ +-----+ +-----+ +-----+ +------+ +------+ +-----+ Legend: IF1 = PC select/update & instruction address generation IF2 = Instruction cache access & instruction buffer/alignment ID = Decode, register read, hazard check EX = Execute (ALU/branch evaluation/address calc) MEM1 = Data cache access (initiate load/store) MEM2 = Data return/commit for memory ops WB = Write back result to register file Pipeline timing (one instruction per cycle after fill): Cycle: 1 2 3 4 5 6 7 8 9 10 I1: IF1 IF2 ID EX MEM1 MEM2 WB I2: IF1 IF2 ID EX MEM1 MEM2 WB I3: IF1 IF2 ID EX MEM1 MEM2 WB I4: IF1 IF2 ID EX MEM1 MEM2 WB
Quick Stage Summary
- IF1: Computes next PC and starts instruction fetch.
- IF2: Reads instruction from I-cache and aligns it.
- ID: Decodes opcode, reads source registers, detects hazards.
- EX: Performs ALU operation or branch decision/address calculation.
- MEM1: Initiates data memory access for load/store.
- MEM2: Completes memory read/write and formats data.
- WB: Writes results back to the destination register.